Clock synchronizing circuit including a voltage controlled oscillator

ABSTRACT

A clock synchronizing circuit separates and filters a clock component from a digital input wave. The output of the circuit is sampled to produce a two-level signal. A voltage controlled oscillator generates a clock signal having a phase and a frequency which is controlled responsive to the two-level signal.

BACKGROUND OF THE INVENTION

The present invention relates to a clock synchronizing circuit and, moreparticularly, to a clock synchronizing circuit for use with ademodulator in a digital carrier wave transmission system.

In a demodulator applicable to a digital carrier wave transmissionsystem, a clock signal must be provided in order that a demodulatedanalog signal may be sampled at optimum points and thereby converted toa digital signal, i.e., a regenerated digital signal. A prior art clocksynchronizing circuit which is adapted for recovery of the clock signalcomprises a clock separating means or clock component producing meansincluding a tank circuit, a limiter, a phase comparator, and a voltagecontrolled oscillator (VCO). The clock separating means separates orproduces a clock component from a digital modulated wave (e.g. PSK waveor QAM wave) or a demodulated analog signal. The limiter is adapted tolimit the amplitude variation of the separated clock component. Thephase comparator compares an output of the limiter and an output of theVCO in terms of phase, producing an error voltage which is proportionalto the phase difference. Controlled by the error voltage, the VCO variesits oscillation frequency until the error voltage becomes minimum, thatis, until a clock signal recovered by the VCO is brought intosynchronism with the separated clock component. The recovered clocksignal which is synchronized, as stated, is used to sample thepreviously mentioned demodulated signal.

The prior art clock synchronizing circuit requires the limiter thereofto be furnished with, among other things, a small amount of AM/PMconversion. It is difficult to realize a limiter with a small amount ofAM/PM conversion, at the present stage of the art. Although such alimiter may be implemented with a high-speed IC gate, it is expensiveand needs precise and difficult to make adjustments.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a clocksynchronization circuit which is capable of producing a clock signalwith a minimum of jitter and without resorting to a limiter circuit,while reducing the circuit size and, therefore, its costs.

A clock synchronizing circuit of the present invention comprises firstmeans for separating a clock component from a digital modulated wave ora demodulated signal of the digital modulated wave and for filtering theclock components. A second means is provided for sampling the output ofthe first means responsive to a given clock signal in order to produce atwo-level signal. A voltage controlled oscillator means generates theclock signal with a phase and a frequency of the voltage controlledoscillator means controlled by the output of the second means.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription taken with the accompanying drawings, in which:

FIG. 1 is a block diagram of a demodulator using a prior art clocksynchronizing circuit;

FIG. 2 is a block diagram of a demodulator using a first embodiment ofthe clock synchronizing circuit in accordance with the presentinvention;

FIG. 3 shows waveforms which are useful for describing the operation ofa flip-flop which is included in the circuit of FIG. 2;

FIG. 4 is a demodulator to which a second embodiment of the presentinvention is applied;

FIG. 5 is a block diagram showing a third embodiment of the presentinvention; and

FIG. 6 is a block diagram showing a fourth embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows a demodulator using a prior art clock synchronizing circuit2. As shown, the clock synchronizing circuit 2 is made up of aquadrature detector 1 for coherently detecting a multi-level quadraturemodulated IF signal (e.g. QAM wave) I. A reference carrier wave isrecovered from signal I to produce baseband signals Bp and Bq. A clocksynchronizing circuit 2 recovers a clock signal C₁ out of the basebandsignals Bp and Bq. Analog-to-digital (A/D) converters 3 and 4 sample andshape, respectively, the baseband signals Bp and Bq in response to theclock signal C₁ to produce data signals Dp and Dq.

The clock synchronizing circuit 2 comprises full-wave rectifier 201 and202 adapted to full-wave rectify the baseband signals Bp and Bq,respectively. An adder 203 mixes the outputs of the rectifiers 201 and202. A tank circuit (or bandpass filter) narrow-band filters an outputof the adder 203. The limiter 205 limits the amplitude of an output ofthe tank circuit 204. The phase comparator 206 compares the phase of anoutput of the limiter 205 and the output of the clock signal C₁. A lowpass filter (LPF) provides for filtering an output of the phasecomparator 206, and feeds the filtered signal into a voltage controlledoscillator (VCO) 208.

In operation, the multi-level baseband signals are non-linearly operatedby the full-wave rectifiers and other circuits. A separated clockcomponent appears at the output terminal of the adder 203. The tankcircuit 204 suppresses, to a certain extent, the jitter which iscontained in the clock component. The jitter which is present in theoutput of the tank circuit 204 consists of an AM component and a PMcomponent. In order that the AM component may be prevented from beingconverted to a PM component due to an imperfection of the subsequentstage of the circuitry, the limiter 205 is provided for suppressing theAM component. The phase comparator 206 compares the phase of the outputof the limiter 205 and the phase of the output of the VCO 208. Theoutput of the phase comparator 206 is applied via the LPF 207 to the VCO208 to control the output phase of the oscillator, so that the outputclock signal C₁ from the VCO 208 is phase-locked to the output of thelimiter 205.

The prior art clock synchronizing circuit which is constructed andoperated, as described above, has the previously stated shortcomings.

FIG. 2 shows a demodulator with a clock synchronizing circuit inaccordance with a first embodiment of the present invention. In FIG. 2,the structural elements which are the same as those of FIG. 1 aredesignated by like reference numerals.

The demodulator comprises a quadrature detector 1 for producing basebandsignals Bp and Bq responsive to an IF signal I. A clock synchronizingcircuit 21, in accordance with the present invention, is adapted torecover a clock signal C₂ from the baseband signals Bp and Bq. The A/Dconverters 3 and 4 are adapted to sample and shape, respectively, thebaseband signals Bp and Bq in response to the clock signal C₂, therebyproducing data signals Dp and Dq.

As shown, the clock synchronizing circuit 21 contains full-waverectifiers 201 and 202, an adder 203 and a tank circuit 204. A D-typeflip-flop 211 has an input terminal D to which a signal prepared bysuperposing a bias voltage Vb onto an output of the tank circuit 204 isapplied. A clock input terminal C receives the clock signal C₂. An LPF207 receives a signal appearing at an output terminal Q of the flip-flop211. A VCO 208 is adapted to produce the clock signal C₂.

The demodulator of FIG. 2 will operate as follows:

The quadrature detector 1 coherently detects the IF signal I to producebaseband signals Bp and Bq which are respectively associated with thequadrature components of the IF signal I. The signals Bp and Bq arerespectively sampled and shaped by the A/D converters 3 and 4 responsiveto the clock signal C₂, thereby being converted to two sequences of datasignals Dp and Dq.

As previously stated in relationship to FIG. 1, the tank circuit 204 ofthe circuit 21 has a clock output component. The DC voltage level of theclock component is adjusted by the bias voltage Vb which is superposedthereon and, then, is sampled by the flip-flop 211 which is timed to theclock signal C₂. The output terminal Q of the flip-flop 211 becomes aONE if the sampled value is greater than a predetermined threshold valueof the flip-flop 211 and a ZERO if the sampled value is below thethreshold.

FIG. 3 shows waveforms which are useful for describing the operation ofthe flip-flop 211 (FIG. 2). As the input at the input terminal D isvaried, as represented by curves a, b and c, the output at the outputterminal Q assumes logical values as shown in Table 1 below.

                  TABLE 1                                                         ______________________________________                                        TERMINAL                                                                      D INPUT  TERMINAL Q OUTPUT                                                    ______________________________________                                        a        ONE & ZERO WITH SAME PROBABILITY                                     b        ONE                                                                  c        ZERO                                                                 ______________________________________                                    

The output at the terminal Q, therefore, represents a phase comparisoncharacteristic which, in turn, is representative of a phase relationshipbetween the input at the terminal D and the clock signal C₂.Consequently, if the Q output of the flip-flop 211 is applied via theLPF 207 to the VCO 208 as a control signal, the clock synchronizingcircuit 21 of FIG. 2 will be normally operable as a clock synchronizingcircuit.

In FIG. 3, it will be apparent that if the DC voltage level of the Dinput of the flip-flop 211 (FIG. 2) has been adjusted to the thresholdlevel, the Q output remains unchanged despite any change in the clockcomponent level of the D input. That is, the inventive sampling means(flip-flop 211) has a limiting function, in addition to the phasecomparing function.

As described above, the clock synchronizing circuit 21 (FIG. 2), inaccordance with the first embodiment, recovers the clock signal C₂ fromthe baseband signals Bp and Bq and suppresses jitter, which is containedin the signal C₂, by the limiting function of the flip-flop 211, as wellas by the action of tank circuit 204 and LPF 207.

FIG. 4 shows a demodulator to which a clock synchronizing circuit isapplied in accordance with a second embodiment of the present invention.In FIG. 4, the structural elements which are the same as those of FIGS.1 and 2 are designated by like reference numerals. As shown, thedemodulator comprises a quadrature detector 1, an inventive clocksynchronizing circuit 22 adapted to recover a clock signal C₃ from an IFsignal I, and A/ D converter 3 and 4 which are adapted to sample andshape baseband signals Bp and Bq in response to the clock signal C₃ tothereby produce data signals Dp and Dq.

The clock synchronizing circuit 22 includes an envelope detector 221which is a substitute for the full-wave rectifiers 201 and 202 and adder203 of FIG. 2.

From a digitally modulated IF signal, a clock component can be separatedby subjecting it to envelope detection or by a similar non-linearoperation. Thus, the envelope detector 221 separates a clock componentfrom an IF signal I. Responsive to the clock component, each of the tankcircuit 204, flip-flop 211, LPF 207 and VCO 208 function in the samemanner, as discussed in relationship to the clock synchronizing circuit21.

As discussed above, the clock synchronizing circuit 22 (FIG. 4), inaccordance with the second embodiment, recovers the clock signal out ofthe IF signal I. The circuit 22, like the circuit 21, is successful insuppressing jitter to a minimum.

Generally, in a phase-locked loop which includes a limiter, the limiterserves as a high gain amplifier when an input signal is absent. In thiscondition, the influence of a leakage from the output of a VCO to theinput of the limiter becomes substantial so that the oscillationfrequency of the VCO is apt to deviate from its center oscillationfrequency. For this reason, in an initial state where an input signalhas been entered, the deviation between the frequency of the inputsignal and the oscillatin frequency of the VCO is so great that asubstantial period of time is needed for pull-in, or tuning, to becompleted.

FIG. 5 incorporates another embodiment of the present invention whichconstitutes a solution to a problem of slow pull-in or tuning. In FIG.5, a clock synchronizing circuit 23 comprises the structural elements ofcircuit 22 of FIG. 4. In addition, signal detector 231 has an outputwhich becomes a ONE when an output of the tank circuit 204 is presentand a ZERO if otherwise. An OR/NOR gate 232 is coupled to an output ofthe signal detector 231. A NOR gate 233 receives an OR output of thegate 232 and an output of the flip-flop 211. A NOR gate 234 is connectedto a NOR output of the gate 232 and to its own output. The outputs ofthe NOR gates 233 and 234 are routed to the LPF 207. The circuit 23further comprises a VCO 235 which is opposite in the polarity of controlvoltage to the VCO 208 of the circuit 22.

In operation, so long as the IF signal I digitally modulated in a normalmanner and the tank circuit 204 produces a clock component (normaloperation), the input to the OR/NOR gate 232 is ZERO so that the outputof the NOR gate 234 is also a ZERO. The output of the NOR gate 233 is aninverted version of the output of the flip-flop 211. In this situation,the clock synchronizing circuit 23 is enabled to operate in the samemanner as the previously discussed circuit 22. Conversely, while theclock output from the tank circuit 204 is absent, the input to theOR/NOR gate 232 is a ONE with the result that the output of the NOR gate233 is a ZERO, which inhibits the output of the flip-flop 211.Meanwhile, because one of the inputs to the NOR gate 234 is a ZERO andthe other input is its own output which is fed back, the output of thegate 234 is held at a certain constant value. This constant output ofthe gate 234 is substantially equal to a voltage which the NOR gate 233produces in a normally operating condition. (If not equal, the outputlevel of the NOR gate 234 is adjustable through an external circuit).The free oscillation frequency of the VCO 235 is, therefore,substantially equal to the frequency which would hold under a normallyoperating condition.

As described above, the clock synchronizing circuit 23, in accordancewith the third embodiment of FIG. 5, operates in the same manner as thecircuit 22 (FIG. 4) for as long as the IF signal I is digitallymodulated in a normal manner. The tank circuit 204 does not produce aclock component for maintaining the frequency of the clock signal C4 atthe free oscillation frequency of the VCO 235. This effectively cutsdown the pull-in time.

FIG. 6 shows a clock synchronizing circuit which recovers a clock signalfrom the baseband signals and shortens the pull-in time. In FIG. 6, theclock synchronizing circuit 24 comprises, in addition to the structuralelements of the circuit 21 of FIG. 2, the signal detector 231, OR/NORgate 232 and NOR gates 233 and 234, which are included in the circuit 23of FIG. 5. The circuit 24 operates in the same manner that the circuit23 operates.

While the present invention has been shown and described in relationshipto a digital carrier transmission system, it will be apparent that it issimilarly applicable to a digital baseband transmission system.

In summary, it will be seen that the present invention provides a clocksynchronizing circuit with a minimum of jitter, without resorting to ahigh-speed IC gate and other expensive elements. This advantage isderived from the use of D-type flip-flop or a similar inexpensivesampling means which also functions as a limiter and a phase comparator.

Those who are skilled in the art will readily perceive how to modify theinvention. Therefore, the appended claims are to be construed to coverall equivalent structures which fall within the true scope and spirit ofthe invention.

What is claimed is:
 1. A clock synchronizing circuit comprising:firstmeans for separating a clock component from a digital modulated wave andfor filtering the clock component, thereby providing an analog clockcomponent; second means comprising a digital flip-flop circuitresponsive to a clock signal for sampling the analog clock componentprovided from said first means to produce a two-level digital signal;and voltage controlled oscillator means responsive to said two-leveldigital signal for generating said clock signal.
 2. A clocksynchronizing circuit as claimed in claim 1, wherein said first meanscomprises an envelope detector for envelope-detecting the digitalmodulated wave, and a tank circuit for filtering an output of saidenvelope detector.
 3. A clock synchronizing circuit as claimed in claim1, wherein said digital flip-flop circuit comprises a D-type flip-flop.4. A clock synchronizing circuit as claimed in claim 1, furthercomprising a signal detector for detecting an output of said firstmeans, and means responsive to an output of said signal detector forselectively applying an output of said second means and a given constantvoltage to said voltage controlled oscillator means.
 5. A clocksynchronizing circuit as claimed in claim 1, wherein said digitalmodulated wave is a QAM wave.
 6. A clock synchronizing circuit asclaimed in claim 1, wherein said digital modulated wave is PSK wave. 7.A clock synchronizing circuit comprising:first means for separating aclock component from a demodulated signal of a digital modulated waveand for filtering the clock component, thereby providing an analog clockcomponent; second means comprising a digital flip-flop circuitresponsive to a clock signal for sampling the analog clock componentprovided from said first means to produce a two-level digital signal;and voltage controlled oscillator means responsive to said two-leveldigital signal for generating said clock signal.
 8. A clocksynchronizing circuit as claimed in claim 7, further comprising aquadrature detector for quadrature-detecting the digital modulated waveto produce the demodulated signal.
 9. A clock synchronizing circuit asclaimed in claim 8, wherein said first means comprises rectifier meansfor respectively full-wave rectifying two demodulated signals which arein an output of said quadrature detector, an adder for combining outputsof said rectifier means, and a tank circuit for filtering an output ofsaid adder to provide said analog clock component.
 10. A clocksynchronizing circuit as claimed in claim 7, wherein said digitalflip-flop circuit comprises a D-type flip-flop.
 11. A clocksynchronizing circuit as claimed in claim 8, further comprisinganalog-to-digital converter means for sampling the respectivelydemodulated signals from said quadrature detector to convert thedemodulated signals to digital signals.
 12. A clock synchronizingcircuit as claimed in claim 7, further comprising a signal detector fordetecting an output of said first means, and means responsive to anoutput of said signal detector for selectively applying an output ofsaid second means and a given constant voltage to said voltagecontrolled oscillator means.
 13. A clock synchronizing circuit asclaimed in claim 7, wherein said digital modulated wave is a QAM wave.14. A clock synchronizing circuit as claimed in claim 7, wherein saiddigital modulated wave is a PSK wave.
 15. A clock synchronizing circuitcomprising detector means responsive to a digital modulated wave forproducing baseband signals, voltage controlled oscillator meansresponsive to a control signal for providing a clock signal, first meanscoupled to said detector means for producing an analog clock componentfrom said digital modulated wave, second means comprising a digitalflip-flop circuit connected to said voltage controlled oscillator meansand said first means for sampling said analog clock component inresponse to said clock signal, and filtering means for providing saidcontrol signal in response to an output of said second means.
 16. Thecircuit of claim 15 wherein said first means comprises a full-waverectifier.
 17. The circuit of claim 15 wherein said first means is anenvelope detector.
 18. The circuit of claim 17 and signal detector meanscoupled to an output of said envelope detector, said second means beinga D-type flip-flop having a D input coupled to an output of said firstmeans, a Q output coupled to an input of said filtering means, and a Cinput coupled to an output of said voltage controlled oscillator. 19.The circuit of claim 17 and signal detector means coupled to an outputof said detector means, said second means being a D-type flip-flophaving a D input coupled to an output of said first means, a Q outputcoupled to an input of said filtering means, and a C input coupled to anoutput of said voltage controlled oscillator.
 20. A clock synchronizingcircuit as claimed in claim 15, wherein said digital modulated wave is aQAM wave.
 21. A clock synchronizing circuit as claimed in claim 15,wherein said digital modulated wave is PSK wave.